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| SPICE Device Model SI2305DS Vishay Siliconix P-Channel 1.25-W, 1.8-V (G-S) MOSFET CHARACTERISTICS * P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model schematic is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71489 07-May-01 www.vishay.com 1 SPICE Device Model SI2305DS Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions VDS = VGS, ID = -250 A VDS -5 V, VGS = -4.5 V VDS -5 V, VGS = -2.5 V VGS = -4.5 V, ID = -3.5 A Typical Unit VGS(th) ID(on) 0.78 77 V A 20 0.044 0.063 0.095 10 0.80 S V Drain-Source On-State Resistance a rDS(on) VGS = -2.5 V, ID = -3.0 A VGS = -1.8 V, ID = -2.0 A Forward Transconductance Diode Forward Voltage a a gfs VSD VDS = -5 V, ID = -3.5 A IS = -1.6 A, VGS = 0 V Dynamic b Total Gate Charge Gate-Source Charge Gate-Drain Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Qg Qgs Qgd Ciss Coss Crss VGS = -4 V, VDS = 0 V, f = 1 MHz VDS = -4 V, VGS = -4.5 V, ID = -3.5 A 9 2 1.5 1237 370 205 pf nC Switching Rise Time c Turn-On Delay Timeb td(on) tr VDD = -4 V, RL = 4 ID -1 A, VGEN = -4.5 V, RG = 6 31 23 ns 54 13 Turn-Off Delay Time Fall Time b td(off) tf Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. For design aid only, not subject to production testing c. Switching time is essentially independent of operating temperature www.vishay.com 2 Document Number: 71489 07-May-01 SPICE Device Model SI2305DS Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 71489 07-May-01 www.vishay.com 3 |
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